;**************************************************** ;** MENES88C.inc ** ;** 16F88 Osc interne= PA6 et PA7 libre pour I/O ** ;** et MCLR sur PA5 ** ;**************************************************** __IDLOCS h'1949' ;Identification en h'2000'=valeur 1 9 4 9 __CONFIG h'2007',h'2F30' ;mot de config en h'2007': ;** osc interne et MCLR sur PA5 = h'3F30' pour avoir sortie osc sur PA6 = h'3F31' ERRORLEVEL -302 ;pour ne pas afficher les warning ERRORLEVEL -305 INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTIONS EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ANSEL EQU H'009B' CMCON EQU H'009C' CVRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- #DEFINE IRP STATUS,7 #DEFINE RP1 STATUS,6 #DEFINE RP0 STATUS,5 #DEFINE TO STATUS,4 #DEFINE PD STATUS,3 #DEFINE Z STATUS,2 #DEFINE DC STATUS,1 #DEFINE C STATUS,0 ;----- INTCON Bits -------------------------------------------------------- #DEFINE GIE INTCON,7 #DEFINE PEIE INTCON,6 #DEFINE TMR0IE INTCON,5 #DEFINE INT0IE INTCON,4 #DEFINE RBIE INTCON,3 #DEFINE TMR0IF INTCON,2 #DEFINE INT0IF INTCON,1 #DEFINE RBIF INTCON,0 ;----- PIR1 Bits ---------------------------------------------------------- #DEFINE ADIF PIR1,6 #DEFINE RCIF PIR1,5 #DEFINE TXIF PIR1,4 #DEFINE SSPIF PIR1,3 #DEFINE CCP1IF PIR1,2 #DEFINE TMR2IF PIR1,1 #DEFINE TMR1IF PIR1,0 ;----- PIR2 Bits ---------------------------------------------------------- #DEFINE OSFIF PIR2,7 #DEFINE CMIF PIR2,6 #DEFINE EEIF PIR2,4 ;----- T1CON Bits --------------------------------------------------------- #DEFINE T1RUN T1CON,6 #DEFINE T1CKPS1 T1CON,5 #DEFINE T1CKPS0 T1CON,4 #DEFINE T1OSCEN T1CON,3 #DEFINE T1SYNC T1CON,2 #DEFINE TMR1CS T1CON,1 #DEFINE TMR1ON T1CON,0 ;----- T2CON Bits --------------------------------------------------------- #DEFINE TOUTPS3 T2CON,6 #DEFINE TOUTPS2 T2CON,5 #DEFINE TOUTPS1 T2CON,4 #DEFINE TOUTPS0 T2CON,3 #DEFINE TMR2ON T2CON,2 #DEFINE T2CKPS1 T2CON,1 #DEFINE T2CKPS0 T2CON,0 ;----- SSPCON Bits -------------------------------------------------------- #DEFINE WCOL SSPCON,7 #DEFINE SSPOV SSPCON,6 #DEFINE SSPEN SSPCON,5 #DEFINE CKP SSPCON,4 #DEFINE SSPM3 SSPCON,3 #DEFINE SSPM2 SSPCON,2 #DEFINE SSPM1 SSPCON,1 #DEFINE SSPM0 SSPCON,0 ;----- CCP1CON Bits ------------------------------------------------------- #DEFINE CCP1X CCP1CON,5 #DEFINE CCP1Y CCP1CON,4 #DEFINE CCP1M3 CCP1CON,3 #DEFINE CCP1M2 CCP1CON,2 #DEFINE CCP1M1 CCP1CON,1 #DEFINE CCP1M0 CCP1CON,0 ;----- RCSTA Bits --------------------------------------------------------- #DEFINE SPEN RCSTA,7 #DEFINE RX9 RCSTA,6 #DEFINE SREN RCSTA,5 #DEFINE CREN RCSTA,4 #DEFINE ADDEN RCSTA,3 #DEFINE FERR RCSTA,2 #DEFINE OERR RCSTA,1 #DEFINE RX9D RCSTA,0 ;----- ADCON0 Bits -------------------------------------------------------- #DEFINE ADCS1 ADCON0,7 #DEFINE ADCS0 ADCON0,6 #DEFINE CHS2 ADCON0,5 #DEFINE CHS1 ADCON0,4 #DEFINE CHS0 ADCON0,3 #DEFINE GO ADCON0,2 #DEFINE ADON ADCON0,0 ;----- OPTION_REG Bits ----------------------------------------------------- #DEFINE RBPU OPTIONS,7 #DEFINE INTEDG OPTIONS,6 #DEFINE T0CS OPTIONS,5 #DEFINE T0SE OPTIONS,4 #DEFINE PSA OPTIONS,3 #DEFINE PS2 OPTIONS,2 #DEFINE PS1 OPTIONS,1 #DEFINE PS0 OPTIONS,0 ;----- PIE1 Bits ---------------------------------------------------------- #DEFINE ADIE PIE1,6 #DEFINE RCIE PIE1,5 #DEFINE TXIE PIE1,4 #DEFINE SSPIE PIE1,3 #DEFINE CCP1IE PIE1,2 #DEFINE TMR2IE PIE1,1 #DEFINE TMR1IE PIE1,0 ;----- PIE2 Bits ---------------------------------------------------------- #DEFINE OSFIE PIE2,7 #DEFINE CMIE PIE2,6 #DEFINE EEIE PIE2,4 ;----- PCON Bits ---------------------------------------------------------- #DEFINE NOT_POR PCON,1 #DEFINE NOT_BOR PCON,0 ;----- OSCCON Bits ------------------------------------------------------- #DEFINE IRCF2 OSCCON,6 #DEFINE IRCF1 OSCCON,5 #DEFINE IRCF0 OSCCON,4 #DEFINE OSTS OSCCON,3 #DEFINE IOFS OSCCON,2 #DEFINE SCS1 OSCCON,1 #DEFINE SCS0 OSCCON,0 ;----- OSCTUNE Bits ------------------------------------------------------- #DEFINE TUN5 OSCTUNE,5 #DEFINE TUN4 OSCTUNE,4 #DEFINE TUN3 OSCTUNE,3 #DEFINE TUN2 OSCTUNE,2 #DEFINE TUN1 OSCTUNE,1 #DEFINE TUN0 OSCTUNE,0 ;----- SSPSTAT Bits ------------------------------------------------------- #DEFINE SMP SSPSTAT,7 #DEFINE CKE SSPSTAT,6 #DEFINE D_A SSPSTAT,5 #DEFINE P SSPSTAT,4 #DEFINE S SSPSTAT,3 #DEFINE R_W SSPSTAT,2 #DEFINE UA SSPSTAT,1 #DEFINE BF SSPSTAT,0 ;----- TXSTA Bits --------------------------------------------------------- #DEFINE CSRC TXSTA,7 #DEFINE TX9 TXSTA,6 #DEFINE TXEN TXSTA,5 #DEFINE SYNC TXSTA,4 #DEFINE BRGH TXSTA,2 #DEFINE TRMT TXSTA,1 #DEFINE TX9D TXSTA,0 ;----- ADCON1 Bits -------------------------------------------------------- #DEFINE ADFM ADCON1,7 #DEFINE ADCS2 ADCON1,6 #DEFINE VCFG1 ADCON1,5 #DEFINE VCFG0 ADCON1,4 ;----- WDTCON Bits -------------------------------------------------------- #DEFINE WDTPS3 WDTCON,4 #DEFINE WDTPS2 WDTCON,3 #DEFINE WDTPS1 WDTCON,2 #DEFINE WDTPS0 WDTCON,1 #DEFINE SWDTEN WDTCON,0 ;----- CMCON Bits --------------------------------------------------------- #DEFINE C2OUT CMCON,7 #DEFINE C1OUT CMCON,6 #DEFINE C2INV CMCON,5 #DEFINE C1INV CMCON,4 #DEFINE CIS CMCON,3 #DEFINE CM2 CMCON,2 #DEFINE CM1 CMCON,1 #DEFINE CM0 CMCON,0 ;----- CVRCON Bits -------------------------------------------------------- #DEFINE CVREN CVRCON,7 #DEFINE CVROE CVRCON,6 #DEFINE CVRR CVRCON,5 #DEFINE CVR3 CVRCON,3 #DEFINE CVR2 CVRCON,2 #DEFINE CVR1 CVRCON,1 #DEFINE CVR0 CVRCON,0 ;----- EECON1 Bits -------------------------------------------------------- #DEFINE EEPGD EECON1,7 #DEFINE FREE EECON1,4 #DEFINE WRERR EECON1,3 #DEFINE WREN EECON1,2 #DEFINE WR EECON1,1 #DEFINE RD EECON1,0 ;****************************************** ;** SP DELAI de 1 ms Fosc de 8 MHz ** ;** utilise 2 cases RAM en h'7B'et h'7C' ** ;****************************************** DEL MOVLW d'10' MOVWF h'7B' DECFSZ h'7B' GOTO $ + 2 GOTO $ + 6 MOVLW d'69' MOVWF h'7C' DECFSZ h'7C' GOTO $ - 1 GOTO $-7 RETURN ;******************************************** ;** SP DELAI de W fois 1 ms ** ;** utilise 1 case RAM en h'7D' ** ;******************************************** DELAI MOVWF h'7D' INCF h'7D' DECFSZ h'7D' GOTO $ + 2 GOTO $ + 3 CALL DEL GOTO $ - 4 RETURN ;******************************************* ;** MACRO ** ;** sauvegarde de W et de STATUS ** ;** utilise 2 cases RAM en h'7E' et h'7F' ** ;******************************************* PUSH MACRO MOVWF h'7F' ; W sauvé en RAM adresse 4F MOVFW STATUS MOVWF h'7E' ; STATUS sauvé en RAM adresse 4E PAGE0 ENDM POP MACRO MOVFW h'7E' MOVWF STATUS ; restaure STATUS SWAPF h'7F',F ; restaure W SWAPF h'7F',W ENDM ;***************************************** PAGE0 MACRO BCF STATUS,6 BCF STATUS,5 ENDM PAGE1 MACRO BCF STATUS,6 BSF STATUS,5 ENDM PAGE2 MACRO BSF STATUS,6 BCF STATUS,5 ENDM PAGE3 MACRO BSF STATUS,6 BSF STATUS,5 ENDM